The present invention relates generally to integrated circuit (IC) designs, and more particularly to a latch type sense amplifier that is insensitive to device mismatch issues.
Sense amplifier (SA) is a basic component that is used for both programming and reading operations for memory devices. During the operation, a typical sense amplifier is turned on in response to the signals on a bit line and its complement. The operation of sense amplifier can be divided into a pre-charge/discharge phase and an evaluation phase. For a conventional voltage-mode sense amplifier, the evaluation speed is proportional to the evaluation chain conductivity and is inversely proportional to its capacitance. The pre-charge speed of the conventional voltage-mode sense amplifier is proportional to the pre-charge transistor conductivity and is inversely proportional to its capacitance. The capacitance of the conventional voltage-mode sense amplifier is a function of the load capacitance, evaluation chain capacitance and pre-charge transistor capacitance.
A latch type sense amplifier typically includes a voltage-mode sense amplifier coupled to a latch. The sense amplifier charges the latch to store a value at its data storage node in response to the bit line signal. The stored value can be reversed when the bit line signal and its complement are switched.
The latch type sense amplifier may fail due to the mismatched devices within its latch. The latch typically is configured by two sets of serially coupled PMOS and NMOS transistors where the PMOS transistors are coupled to a power supply and the NMOS transistors are coupled to the sense amplifier. During the operation, the bit line signal and its complement activate the sense amplifier to selectively charge or discharge the storage nodes through the NMOS transistors. Due to reasons, such as fabrication process variation, the two NMOS transistors can have mismatched electric characteristics, such as different threshold voltages. This can significantly delay the time for the sense amplifier to access the storage nodes of the latch. Moreover, as the semiconductor devices continue to shrink in size, the NMOS transistors within the latch becomes increasingly susceptible to process variation, thereby resulting in a higher chance of mismatch.
Thus, it is desirable to have a latch type sense amplifier that is insensitive to the device mismatch issues.